A novel memory size model for variable-mapping in system level design”, ASPDAC 2004

Abstract — It is predicted that 70 % of the chip area will be occupied by memories in future system-on-chips. The minimization of on-chip memory hence becomes increasingly important for cost, performance and energy consumption. This paper proposes a novel memory size model for algorithms which map the variables of a system behavior to memories of a sys-tem architecture. To our knowledge, it is the first memory estimation approach that analyzes the vari-able lifetime for the system behavior, which consists of hierarchically-modelled and concurrently-executed processes and contains variables with different sizes. Experimental results show that significant improve-ments can be achieved. I